... collaborate with the Foundry Process Engineer, SoC Architect, Microarchitecture, Packaging, ... integration, partitioning, chip level clock planning, bump placement / RDL routing, ... chip STA timing, DFT strategy planning, and final physical verification. Good ...
25 days ago
... working collaboratively within a team of engineers who design and deliver innovative ... and market leading engineered solutions for the industry. Your ... client management skills, and service planning. Responsibilities Build strong & open ...
26 days ago