Description:
Join one of the most technically advanced FPGA teams in Australia, designing cutting-edge systems where you'll be working on high-performance, timing-critical designs.This is a role for engineers who enjoy pushing FPGAs to their limits—where MHz matter, timing margins are tight, and LUTs must be used with precision.
This is a senior position and requires you to have 10+ years FPGA design experience.
What You’ll Work On:
- Architect and implement FPGA designs running at higher clock frequencies, with strict timing and deterministic performance requirements.
- Optimise datapaths for throughput and latency, balancing pipeline depth and logic resource usage (LUTs, FFs, DSPs).
- Drive the complete design cycle—from RTL through synthesis, timing closure, and lab validation on real hardware.
- Debug complex interactions between FPGAs, high-speed memory interfaces (DDR3/DDR4)
- Collaborate with a multidisciplinary team of hardware, software, and systems engineers on highly integrated products.
- Excellent knowledge in VHDL or Verilog, with the ability to write RTL that synthesises cleanly and predictably at higher clock rates.
- Deep understanding of synchronous design techniques, clock domain crossing, and how to meet timing at high utilisation.
- Familiarity with Vivado timing analysis, floorplanning, ILA debugging, and scripting (Tcl/Python) for build/test automation.
- Hands-on with hardware validation and system-level debugging in the lab using scopes, analysers, and JTAG tools.
- The position is based in Sydney CBD
- Offering an excellent salary package depending on your level of experience
- Permanent residency or citizenship preferred, but sponsorship is available for standout candidates
- Onsite or video interviews available
Luke Johnson
Recruitment Consultant
P: 0466 210 441
E: luke@codematix.com.au
You can find out more about Codematix Pty. Ltd. by visiting codematix.com.au
12 May 2025;
from:
uworkin.com